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Proceedings Paper

Avalanche photodiode array in BiCMOS technology
Author(s): Alice Biber; Peter Seitz
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Paper Abstract

Avalanche photodiode (APD) imaging arrays offering programmable gain are a long awaited achievement in electronic imaging. In view of the recent boom in CMOS imaging, a logical next step for increasing responsivity was to integrate APDs in CMOS. Once the feasibility of these diodes has been prove, we can combine the devices with control and readout circuitry, thus creating an integrated 2D APD array. Such arrays exploit the sub-Geiger mode, where the applied voltage is just slightly less than the breakdown voltage. The diodes used in the 2D array were implemented in a standard 2 micrometers BiCMOS process. To keep the readout circuitry simple, a small transimpedance amplifier has been designed, taking into account that there is a significant trade off between noise performance and silicon area. A with other CMOS imagers, we use a random access active pixel sensor readout. The compete imaging array consists of 12 by 24 pixels, each of size 71.5 micrometers by 154 micrometers to fit on a 5 mm2 chip. First images prove the feasibility of avalanche photodiode imaging using standard BiCMOS technology. Thus important data to improve sensor operation has been collected. The complexity of the imager design is increased by special noise and high voltage requirements. Area and calibration restrictions must be considered also for this photo-sensor array.

Paper Details

Date Published: 27 April 1999
PDF: 10 pages
Proc. SPIE 3649, Sensors, Cameras, and Systems for Scientific/Industrial Applications, (27 April 1999); doi: 10.1117/12.347083
Show Author Affiliations
Alice Biber, Ctr. Suisse d'Electronique et de Microtechnique (Switzerland)
Peter Seitz, Ctr. Suisse d'Electronique et de Microtechnique (Switzerland)

Published in SPIE Proceedings Vol. 3649:
Sensors, Cameras, and Systems for Scientific/Industrial Applications
Morley M. Blouke; George M. Williams, Editor(s)

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