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Proceedings Paper

Layout-based manufacturability assessment and yield prediction methodology
Author(s): Paul Simon; Kees Veelenturf; Paul van Adrichem; Jeroen de Jong; Stanley Sprij; Wojciech P. Maly
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Paper Abstract

This paper describes an automated manufacturability assessment and yield prediction software platform that has been developed, installed and used in a semiconductor manufacturing environment. the system is applied to characterize all incoming new products by extracting a large number of design attributes from their layout. Be checking the similarity to products that have already shown acceptable levels of yield, the risk of starting high volume production for new products is evaluated. The system also accurately predicts product yield on functional-block and layer level which is indispensable for the understanding of product dependent yield loss and rapid yield learning. The system proves to be a very valuable addition to the conventional yield analysis methodologies.

Paper Details

Date Published: 27 April 1999
PDF: 7 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346928
Show Author Affiliations
Paul Simon, Philips Semiconductors (Netherlands)
Kees Veelenturf, Philips Semiconductors (Netherlands)
Paul van Adrichem, Philips Semiconductors (Netherlands)
Jeroen de Jong, Philips Semiconductors (Netherlands)
Stanley Sprij, Philips Semiconductors (Netherlands)
Wojciech P. Maly, Carnegie Mellon Univ. (United States)

Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)

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