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Proceedings Paper

Floorplanning of memory ICs: routing complexity vs. yield
Author(s): Israel Koren; Zahava Koren
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Paper Abstract

It has recently been shown that for very large chips, especially those with some incorporated redundancy, the chip's floorplan may affect its yield. When selecting a floorplan, the designer should, therefore, consider the expected yield in addition to the traditional objectives such as area, performance, and routing complexity. This paper studies the two seemingly unrelated objectives of routing complexity minimization and yield maximization, and justifies the need for a trade-off analysis when determining the floorplan. We will focus on the analysis of large memory ICs with redundant modules, for which several alternative floorplans may exist.

Paper Details

Date Published: 27 April 1999
PDF: 8 pages
Proc. SPIE 3743, In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing, (27 April 1999); doi: 10.1117/12.346926
Show Author Affiliations
Israel Koren, Univ. of Massachusetts/Amherst (United States)
Zahava Koren, Univ. of Massachusetts/Amherst (United States)


Published in SPIE Proceedings Vol. 3743:
In-Line Characterization, Yield Reliability, and Failure Analyses in Microelectronic Manufacturing
Kostas Amberiadis; Gudrun Kissinger; Katsuya Okumura; Seshu Pabbisetty; Larg H. Weiland, Editor(s)

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