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Proceedings Paper

Characterization of gate electrode etch process for 0.25 um extended to 0.18 um
Author(s): Henry Gerung; Vijay Chhagan; Pradeep R. Yelehanka; Mei-Sheng Zhou; Joe K. Hui
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Paper Abstract

With shrinking dimension of the transistor gate, the gate profile and line dimension control requirement becomes more stringent. LPCVD (Low Pressure Chemical Vapor Deposition) polysilicon is used as the gate material with thermally grown thin nitrided gate oxide. Bottom Anti-Reflective Coating is used together with Deep UV resist for patterning. After etch, footing at the gate bottom is observed and the resulting in-line line width has a large degree of non- uniformity. These phenomena are found on both 0.25 micrometers and 0.18 micrometers structure. In this paper, we present the application of Design of Experiment principle in solving footing problem at the bottom of the gate polysilicon and obtaining better in-line control.

Paper Details

Date Published: 23 April 1999
PDF: 9 pages
Proc. SPIE 3742, Process and Equipment Control in Microelectronic Manufacturing, (23 April 1999); doi: 10.1117/12.346233
Show Author Affiliations
Henry Gerung, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Vijay Chhagan, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Pradeep R. Yelehanka, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Mei-Sheng Zhou, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Joe K. Hui, Chartered Semiconductor Manufacturing Ltd. (Singapore)


Published in SPIE Proceedings Vol. 3742:
Process and Equipment Control in Microelectronic Manufacturing
Kevin Yallup; Murali K. Narasimhan, Editor(s)

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