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Proceedings Paper

Parallel architectures for optoelectronic VLSI processing
Author(s): Dietmar Fey; Guido Grimm; Werner Erhard
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Paper Abstract

Limited bandwidth because of too few and too slow external pins is one of the major problems in current VLSI systems. Increasing clock rates and the growing transistor density in future microprocessor will enlarge the imbalance between satisfying computing power and insufficient communication performance. Optoelectronic VLSI (OE-VLSI) circuits using highly dense 3D optical interconnections offer the potential to overcome these problems. To lead OE-VLSI processing to success it is necessary to point out a diversity of architectures that profit extremely from a 2D optical input/output interface. Such architectures have to be developed especially for an optoelectronic solution. We demonstrate this for various architectures like binary neural associative memories and fine-grain 3D processor cores for integer and digital signal processing. We specify the electronic circuits and the optical interconnection schemes. We found out that an optoelectronic approach for the associative memory offers two orders of magnitude more performance than all-electronic solutions. The stacked 3D integer processor offers a performance increase of about 10 to 50 over current RISC processors. For the realization of the OE-VLSI circuits we developed a CMOS-SEED chip and a smart detector test chip consisting of CMOS circuitry monolithically integrated with a silicon based array of photo diodes.

Paper Details

Date Published: 13 April 1999
PDF: 12 pages
Proc. SPIE 3632, Optoelectronic Interconnects VI, (13 April 1999); doi: 10.1117/12.344630
Show Author Affiliations
Dietmar Fey, Friedrich-Schiller Univ.-Jena (Germany)
Guido Grimm, Friedrich-Schiller Univ.-Jena (Germany)
Werner Erhard, Friedrich-Schiller Univ.-Jena (Germany)


Published in SPIE Proceedings Vol. 3632:
Optoelectronic Interconnects VI
Julian P. G. Bristow; Suning Tang, Editor(s)

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