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Proceedings Paper

Description and practical uses of IBM ZISC036
Author(s): Robert David; Erin Williams; Ghislain de Tremiolles; Pascal Tannhof
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Paper Abstract

In this paper, we will describe the basic features and capabilities of the IBM ZISC036, a massively parallel chip which implements the Restricted Coulomb Energy algorithm and the K-Nearest Neighbor algorithm. Both of the aforementioned algorithms, their learning and recognition phases, and the basic architectural structure of this hardware implementation will be discussed. The ZISC036 chip containing thirty-six neurons has the advantages of processing time reduction in comparison with classical models, adaptability, and pattern learning,; it is both easy to program and operate. A neuron is a processor capable of prototype and associated information storage as well as distance computation and communication with other neurons. At the end of this paper to show the advantage of this model and illustrate the principle of the ZISC, we will present two applications of the ZISC, one for image contour extraction, and the other for visual probe mask inspection on wafers.

Paper Details

Date Published: 22 March 1999
PDF: 14 pages
Proc. SPIE 3728, Ninth Workshop on Virtual Intelligence/Dynamic Neural Networks, (22 March 1999); doi: 10.1117/12.343038
Show Author Affiliations
Robert David, IBM France (France)
Erin Williams, IBM France (United States)
Ghislain de Tremiolles, IBM France (France)
Pascal Tannhof, IBM France (France)


Published in SPIE Proceedings Vol. 3728:
Ninth Workshop on Virtual Intelligence/Dynamic Neural Networks

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