Share Email Print

Proceedings Paper

Generic VHDL implementation of a PCNN with loadable coefficients
Author(s): Mikael Millberg; Johnny Oberg; Joakim T. A. Waldemark
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper presents a general VHDL implementation of a Pulse Coupled Neural Network. The VHDL implementation is targeted for FPGA but can also be used with advantage for ASIC implementations. This particular case deals with images of the size 128 X 128 pixels coming at a rate of 60 images per second, each image iterated by the PCNN 70 times, i.e. a real time image processing system. Thanks to the generality, this suggested solution can easily be transformed into, e.g., a solution with images sized 32 X 32 pixels, coming at a speed of 960 images per second, assuming the same iteration length. The hardware requirement and problems are analyzed and solutions are proposed. Some problems that are dealt with are: the huge amount of data produced, the high throughput (i.e. the rate of new data produced) and the loading of coefficients during runtime.

Paper Details

Date Published: 22 March 1999
PDF: 12 pages
Proc. SPIE 3728, Ninth Workshop on Virtual Intelligence/Dynamic Neural Networks, (22 March 1999); doi: 10.1117/12.343037
Show Author Affiliations
Mikael Millberg, Royal Institute of Technology (Sweden)
Johnny Oberg, Royal Institute of Technology (Sweden)
Joakim T. A. Waldemark, Royal Institute of Technology (Sweden)

Published in SPIE Proceedings Vol. 3728:
Ninth Workshop on Virtual Intelligence/Dynamic Neural Networks
Thomas Lindblad; Mary Lou Padgett; Jason M. Kinser, Editor(s)

© SPIE. Terms of Use
Back to Top