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Proceedings Paper

Effect of polysilicon interface on stress in multistacked polysilicon films
Author(s): Chang-Auck Choi; Chang Seung Lee; Won-Ick Jang; Jong-Hyun Lee; Byung-Ki Shon
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Paper Abstract

In this paper, we present a detailed study of the effect of the interface in multi-stacked polysilicon film. In order to investigate microstructural stress characteristics, we fabricated laminated type 2 micrometers thickness of polysilicon test structures such as bridges and rotating beam pairs. Also the characteristics of the various doping and deposition method, and annealing treatment are examined through the SIMS analysis. The relative interface location was carried by changing the film thickness for each deposition step and this was compared with 2 micrometers thick film deposited at a time. We found that the interface is one of the key factors deciding the stress gradient in multi- stacked polysilicon film but the residual stress is independent of the interface location. Finally, on the basis of the result, fabricated a test pattern of the multi- stacked polysilicon microstructure with thickness of 6.5 micrometers using the symmetrical stacking and doping method has a low stress of 7.6 MPa and a low stress gradient of -0.15 MPa/micrometers .

Paper Details

Date Published: 10 March 1999
PDF: 7 pages
Proc. SPIE 3680, Design, Test, and Microfabrication of MEMS and MOEMS, (10 March 1999); doi: 10.1117/12.341186
Show Author Affiliations
Chang-Auck Choi, Electronics and Telecommunications Research Institute (South Korea)
Chang Seung Lee, Electronics and Telecommunications Research Institute (South Korea)
Won-Ick Jang, Electronics and Telecommunications Research Institute (South Korea)
Jong-Hyun Lee, Electronics and Telecommunications Research Institute (South Korea)
Byung-Ki Shon, Kyungbook National Univ. (South Korea)


Published in SPIE Proceedings Vol. 3680:
Design, Test, and Microfabrication of MEMS and MOEMS

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