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Proceedings Paper

Media processing with field-programmable gate arrays on a microprocessor's local bus
Author(s): V. Michael Bove; Mark Lee; Yuan-Min Liu; Christopher McEniry; Thomas A. Nwodoh; John A. Watlington
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Paper Abstract

The Chidi system is a PCI-bus media processor card which performs its processing tasks on a large field-programmable gate array (Altera 10K100) in conjunction with a general purpose CPU (PowerPC 604e). Special address-generation and buffering logic (also implemented on FPGAs) allows the reconfigurable processor to share a local bus with the CPU, turning burst accesses to memory into continuous streams and converting between the memory's 64-bit words and the media data types. In this paper we present the design requirements for the Chidi system, describe the hardware architecture, and discuss the software model for its use in media processing.

Paper Details

Date Published: 21 December 1998
PDF: 7 pages
Proc. SPIE 3655, Media Processors 1999, (21 December 1998); doi: 10.1117/12.334768
Show Author Affiliations
V. Michael Bove, MIT Media Lab. (United States)
Mark Lee, MIT Media Lab. (United States)
Yuan-Min Liu, MIT Media Lab. (United States)
Christopher McEniry, MIT Media Lab. (United States)
Thomas A. Nwodoh, MIT Media Lab. (United States)
John A. Watlington, MIT Media Lab. (United States)

Published in SPIE Proceedings Vol. 3655:
Media Processors 1999
Sethuraman Panchanathan; Subramania I. Sudharsanan; V. Michael Bove, Editor(s)

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