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Proceedings Paper

Hardware/software design implementation of feature detection for a reconfigurable processor
Author(s): Philip P. Dang; Paul M. Chau
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Paper Abstract

Image processing algorithms are suitable for reconfigurable architectures due to their matrix structures, inherent parallelism and need for flexibility and processing speed. This paper describes a method to implement feature detection on the ReConfigurable Processor (RCP). The RCP is an FPGA- based system, which was built by the VLSI-RCP Research Group at UCSD and L3 Communications. The design is based on the Altera FLEX 10K70. The architecture used to implement feature detector on RCP, software and hardware implementation will be discussed.

Paper Details

Date Published: 28 December 1998
PDF: 9 pages
Proc. SPIE 3653, Visual Communications and Image Processing '99, (28 December 1998); doi: 10.1117/12.334727
Show Author Affiliations
Philip P. Dang, Univ. of California/San Diego (United States)
Paul M. Chau, Univ. of California/San Diego (United States)


Published in SPIE Proceedings Vol. 3653:
Visual Communications and Image Processing '99
Kiyoharu Aizawa; Robert L. Stevenson; Ya-Qin Zhang, Editor(s)

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