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Proceedings Paper

Error detection and correction in an optoelectronic memory system
Author(s): Robert Hofmann; Madhulima Pandey; Steven Peter Levitan; Donald M. Chiarulli
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Paper Abstract

This paper describes the implementation of error detection and correction logic in the optoelectronic cache memory prototype at the University of Pittsburgh. In this project, our goal is to integrate a 3-D optical memory directly into the memory hierarchy of a personal computer. As with any optical storage system, error correction is essential to maintaining acceptable system performance. We have implemented a fully pipelined, real time decoder for 60-bit Spectral Reed-Solomon code words. The decoder is implemented in reconfigurable logic, using a single Xilinx 4000-series FPGA per code word and is fully scalable using multiple FPGA's. The current implementation operates at 33 Mhz, and processes two code words in parallel per clock cycle for an aggregate data rate of 4 Gb/s. We present a brief overview of the project and of Spectral Reed-Solomon codes followed by a description of our implementation and performance data.

Paper Details

Date Published: 5 November 1998
PDF: 9 pages
Proc. SPIE 3468, Advanced Optical Memories and Interfaces to Computer Storage, (5 November 1998); doi: 10.1117/12.330404
Show Author Affiliations
Robert Hofmann, Univ. of Pittsburgh (United States)
Madhulima Pandey, Univ. of Pittsburgh (United States)
Steven Peter Levitan, Univ. of Pittsburgh (United States)
Donald M. Chiarulli, Univ. of Pittsburgh (United States)


Published in SPIE Proceedings Vol. 3468:
Advanced Optical Memories and Interfaces to Computer Storage
Pericles A. Mitkas; Zameer U. Hasan, Editor(s)

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