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Proceedings Paper

Formal specification and verification of hardware designs
Author(s): S. Ramesh; S.S.S.P Rao; G. Sivakumar; Purandar Bhaduri
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Paper Abstract

Designing modern processors is a great challenges as they involve millions of components. Traditional techniques of testing and simulation do not suffice as the amount of testing required is quite enormous. Design verification is an effective alternative technique for increasing the confidence in the design. Formal verification involves checking whether the system being verified behaves as per the specification using mathematical techniques. In this paper we describe some techniques for enhancing the use of formal methods for the specification and verification of hardware system. We examine how the language Esterel can be used to specify and verify properties of pipelined microprocessor. We also discuss methods for taking hardware descriptions of simple circuits written in VHDL and automatically generating the inputs needed by a theorem prover to prove properties of the circuit.

Paper Details

Date Published: 1 September 1998
PDF: 8 pages
Proc. SPIE 3412, Photomask and X-Ray Mask Technology V, (1 September 1998); doi: 10.1117/12.328817
Show Author Affiliations
S. Ramesh, Indian Institute of Technology (India)
S.S.S.P Rao, Indian Institute of Technology (India)
G. Sivakumar, Indian Institute of Technology (India)
Purandar Bhaduri, Tata Infotech Ltd. (India)


Published in SPIE Proceedings Vol. 3412:
Photomask and X-Ray Mask Technology V
Naoaki Aizaki, Editor(s)

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