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Proceedings Paper

Alternative approaches implementing high-performance FIR filters on lookup-table-based FPGAs: a comparison
Author(s): Tien-Toan Do; Holger Kropp; Carsten Reuter; Peter Pirsch
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Paper Abstract

Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper. Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.

Paper Details

Date Published: 8 October 1998
PDF: 7 pages
Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); doi: 10.1117/12.327043
Show Author Affiliations
Tien-Toan Do, Univ. of Hannover (Germany)
Holger Kropp, Univ. of Hannover (Germany)
Carsten Reuter, Univ. of Hannover (Germany)
Peter Pirsch, Univ. of Hannover (Germany)

Published in SPIE Proceedings Vol. 3526:
Configurable Computing: Technology and Applications
John Schewel, Editor(s)

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