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Proceedings Paper

Minimum multiplicative complexity implementation of the 2D DCT using Xilinx FPGAs
Author(s): Chris H. Dick
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Paper Abstract

This paper investigates two options for the field programmable gate array (FPGA) implementation of a very high-performance 2D discrete cosine transform (DCT) processor for real-time applications. The first architecture exploits the transform separability and uses a row-column decomposition. The row and column processors are realized using distributed arithmetic (DA) techniques. The second approach uses a naturally 2D method based on polynomial transforms. The paper provides an overview of the DCT calculation using DA methods and describes the FPGA implementation. A tutorial overview of a computationally efficient method for computing 2D DCTs using polynomial transforms is presented. A detailed analysis of the datapath for this approach using an 8 X 8 data-set is given. Comparisons are made that show the polynomial transform approach to require 67% of the logic resources of a DA processor for equal throughputs. The polynomial transform approach is also shown to scale better with increasing block size than the DA approach.

Paper Details

Date Published: 8 October 1998
PDF: 12 pages
Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); doi: 10.1117/12.327032
Show Author Affiliations
Chris H. Dick, Xilinx Inc. (United States)


Published in SPIE Proceedings Vol. 3526:
Configurable Computing: Technology and Applications
John Schewel, Editor(s)

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