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Proceedings Paper

Abstract models of reconfigurable architectures for synthesis and compilation
Author(s): Ranga Vemuri; Jeff Walrath
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Paper Abstract

We propose a methodology for specifying abstract models of reconfigurable architectures. These models may be used by compilers, synthesis systems and other design agents to evaluate the correctness and performance of postulated reconfiguration schedules. We show how the proposed methodology can be used to model reconfigurable computation, interconnect, memory and I/O elements interacting with each other using various protocols. We illustrate the modeling approach through small case studies. The proposed methodology is embedded in a modeling language called PDL+ and its support environment called ARC.

Paper Details

Date Published: 8 October 1998
PDF: 14 pages
Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); doi: 10.1117/12.327030
Show Author Affiliations
Ranga Vemuri, Univ. of Cincinnati (United States)
Jeff Walrath, Univ. of Cincinnati (United States)

Published in SPIE Proceedings Vol. 3526:
Configurable Computing: Technology and Applications
John Schewel, Editor(s)

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