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Proceedings Paper

Low-cost reconfigurable DSP-based parallel image processing computer
Author(s): Ciaron W. Murphy; David Mark Harvey; Laurence J. Nicolson
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Paper Abstract

To develop a cost-effective re-configurable DSP engine, it has been proposed to upgrade an existing custom designed TMS320C40 based multi-processing architecture with run-time configuration capabilities. The upgrade will consist of four Xilinx XC6200 series field programmable gate arrays which will enable concurrent algorithm structures to be efficiently mapped onto the system. Furthermore, the upgraded architecture will provide a platform for the development of adaptive routing structures, self- configuration techniques and facilitate the merging of instruction and hardware based parallelism.

Paper Details

Date Published: 8 October 1998
PDF: 11 pages
Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); doi: 10.1117/12.327028
Show Author Affiliations
Ciaron W. Murphy, Liverpool John Moores Univ. (United Kingdom)
David Mark Harvey, Liverpool John Moores Univ. (United Kingdom)
Laurence J. Nicolson, dB Research Ltd. (United Kingdom)


Published in SPIE Proceedings Vol. 3526:
Configurable Computing: Technology and Applications
John Schewel, Editor(s)

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