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Proceedings Paper

Low-power high-performance approach for time-frequency/time-scale computations
Author(s): Bruce W. Suter; Kenneth S. Stevens
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Paper Abstract

This paper presents an application of formal mathematics to create a high performance, low power architecture for time-frequency and time-scale computations implemented in asynchronous circuit technology that achieves significant power reductions and performance enhancements over more traditional approaches. Utilizing a combination of concepts from multivariate signal processing and asynchronous circuit design, a case study is presented dealing with a new architecture for the fast Fourier transform, an algorithm that requires globally shared results. Then, the generalized distributive law is presented an important paradigm for advanced asynchronous hardware design.

Paper Details

Date Published: 2 October 1998
PDF: 5 pages
Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); doi: 10.1117/12.325727
Show Author Affiliations
Bruce W. Suter, Air Force Research Lab. (United States)
Kenneth S. Stevens, Intel Strategic CAD Labs. (United States)


Published in SPIE Proceedings Vol. 3461:
Advanced Signal Processing Algorithms, Architectures, and Implementations VIII
Franklin T. Luk, Editor(s)

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