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Proceedings Paper

Construction of low-complexity highly efficient deterministic modulation codes with adjustable codeword length and error control capability
Author(s): Anthony G. Bessios
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Paper Abstract

Run-length limited RLL(0,k) modulation or k-constrained codes are being used in optical and magnetic recording systems. In this paper a new methodology for the construction of highly efficient modulation codes and in particular new enhanced RLL(0,k) coding schemes are presented. The new methodology generates modulation codes computationally simpler than the existing ones, empowered with partial error detection (PED) capability at the demodulator for improved error control reliability. An increased list of constraints is formed, rather than just constraints pertaining to d, k, I only. Even though concatenation of conventional RLL with ECC can reduce the effectiveness of the ECC, especially with a sliding block encoder/decoder subject to error propagation, a concatenated PED capability can boost the outer ECC performance. Note that in current system using low redundancy ECC, the overall rate is mainly determined by the modulation code rate which critically is to be maintained high. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are achievable. The proposed fixed length block decodable RLL/PED, are generalized schemes of the type: n/n + 1(d equals 0, k equals n - 1/I equals n), and n/n + 1(d equals 0, k equals(n/2/I equals n) where n (epsilon) (Zeta) $GREG5. The encoding/decoding/error-control equations and the global k and interleave I-constraints, are expressed as functions of n, so that fixed encoder/decoder/error-control architectures are obtained in terms of any adjustable work length n, and consequently any code rate n/n + 1. They are characterized by computational simplicity irrespective of the codeword length n, or the code rate. Applicability of the proposed methodology in the construction of Maximum Transition Run codes, is also addressed.

Paper Details

Date Published: 2 October 1998
PDF: 13 pages
Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); doi: 10.1117/12.325719
Show Author Affiliations
Anthony G. Bessios, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 3461:
Advanced Signal Processing Algorithms, Architectures, and Implementations VIII
Franklin T. Luk, Editor(s)

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