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Proceedings Paper

Accelerating run-time reconfiguration on custom computing machines
Author(s): J.-P. Heron; Roger F. Woods
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Paper Abstract

Custom computers comprising of a host processor and FPGAs have been proposed to accelerate computationally complex problems. Whilst the FPGA implementation might be considerably faster than its microprocessor counterpart, this performance acceleration can be degraded by the time to reconfigure the FPGA hardware.This paper demonstrates a technique for developing circuits that can reduce the reconfiguration overhead. Circuits for three basic arithmetic functions multiplication, division and square root have been developed using the Xilinx XC6200 reconfigurable FPGA family. Reconfiguration times have been measured by downloading the designs to the VCC HOTWorks custom computing board. A reduction in reconfiguration time of up to 75 percent has been demonstrated using this design approach.

Paper Details

Date Published: 2 October 1998
PDF: 13 pages
Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); doi: 10.1117/12.325718
Show Author Affiliations
J.-P. Heron, Queen's Univ. of Belfast (Ireland)
Roger F. Woods, Queen's Univ. of Belfast (United Kingdom)

Published in SPIE Proceedings Vol. 3461:
Advanced Signal Processing Algorithms, Architectures, and Implementations VIII
Franklin T. Luk, Editor(s)

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