Share Email Print

Proceedings Paper

Flagged prefix adder for dual additions
Author(s): Neil Burgess
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more than one result per operation. The modified adder, called a 'flagged prefix adder', adds two 2's-complement numbers to give a sum S equals A + B but returns anyone of the following results: S; S + 1; -(S + 1); -(S + 2) as a function of a set of flag bits derived by the adder concurrently with the addition. Similarly, if the flagged prefix adder preforms the 2's-complement subtraction S equals A-B, the adder may return any one of: S, S- 1, -S, -(S + 1). Hence, the flagged prefix adder may be used to perform 'instant increment' or 'instant complement' operations. The extra logic required by the flagged prefix adder relative to the original prefix adder is 2w gates and w 2-to-1 multiplexers.

Paper Details

Date Published: 2 October 1998
PDF: 9 pages
Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); doi: 10.1117/12.325715
Show Author Affiliations
Neil Burgess, Univ. of Adelaide (United Kingdom)

Published in SPIE Proceedings Vol. 3461:
Advanced Signal Processing Algorithms, Architectures, and Implementations VIII
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top