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Proceedings Paper

Novel method to quantify defect-limited yield loss mechanisms on a mixed-mode analog/digital process
Author(s): Sandra Healy
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Paper Abstract

Defects inherent in fab processes limit achievable yields. To improve defect limited yield, it is necessary to identify which defect types contribute most to yield loss and focus resources on reducing those defect types. For memory processes, the standard approach is to utilize the bitmap ability of the products in conjunction with in-line defect data to identify which defects are contributing most to yield los. For wafer fabs producing analog circuitry, in the absence of a suitable bitmapable memory product, an alternative method of quantifying defect limited yield loss mechanisms is required. This paper describes the development and verification of such a method on a mixed mode analog/digital 0.6um CMOS process. This is based on a 'smart' in-line defect classification system in which the likelihood of a defect presence causing a failure is coded. The approach is developed and verified using a mixed mode product that has a section of bitmapable memory. The 'yield prediction' ability of the in-line classification system alone is investigated.

Paper Details

Date Published: 27 August 1998
PDF: 8 pages
Proc. SPIE 3509, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing II, (27 August 1998); doi: 10.1117/12.324411
Show Author Affiliations
Sandra Healy, Analog Devices (Ireland)


Published in SPIE Proceedings Vol. 3509:
In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing II
Sergio A. Ajuria; Tim Z. Hossain, Editor(s)

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