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Proceedings Paper

Simulation of charging voltages on a wafer during plasma etch
Author(s): M. Oner; Bharat L. Bhuva; P. Sisterhen; H. Hasan; Sherra E. Kerns
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Paper Abstract

During plasma etching, the dependence of gate oxide damage on die location and polarity of the charging voltage will yield devices with varying damage across a wafer. This paper describes a simulator capable of estimating the charging voltage across the gate oxide for any location on a wafer. This tool will enable reliability and process engineers to monitor the damage and identify regions of worst-case damage on a wafer for further testing.

Paper Details

Date Published: 28 August 1998
PDF: 4 pages
Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324389
Show Author Affiliations
M. Oner, Vanderbilt Univ. (United States)
Bharat L. Bhuva, Vanderbilt Univ. (United States)
P. Sisterhen, Vanderbilt Univ. (United States)
H. Hasan, Vanderbilt Univ. (United States)
Sherra E. Kerns, Vanderbilt Univ. (United States)


Published in SPIE Proceedings Vol. 3510:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV
Sharad Prasad; Hans-Dieter Hartmann; Tohru Tsujide, Editor(s)

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