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Proceedings Paper

Influence of silicon surface integrity on device yield
Author(s): Yasuhiro Kimura; Hideki Naruoka; Morihiko Kume; Toshiharu Katayama; Hidekazu Yamamoto; Yoji Mashiko
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Paper Abstract

We have investigated the influence of silicon surface integrity (SSI) on LSI device characteristics and yield. It was found that SSI spoiling during the wafer shaping process causes the reduction of gate oxide integrity (GOI), resulting in poor yield of LSIs. We demonstrated that some analysis techniques, such as long-time SC-1 cleaning, the combination of Cu decoration method and SEM observation and optical shallow defect analyzer are effective for evaluation of SSI. By Cu decoration and SEM observation, many small pits of about 0.03 micrometers were observed at GOI failure points. In addition, a model for pit generation was also established in this study. It is thought that Cu ions from contamination takes electrons from activated Si surface in pure water, and oxidized the Si surface partly. The Cu was removed by SC-1 final cleaning, and only pits remain on the Si wafer surface. The pits were primary cause of GOI failure and abnormal LPD increase.

Paper Details

Date Published: 28 August 1998
PDF: 10 pages
Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324374
Show Author Affiliations
Yasuhiro Kimura, Mitsubishi Electric Corp. (Japan)
Hideki Naruoka, Mitsubishi Electric Corp. (Japan)
Morihiko Kume, Mitsubishi Electric Corp. (Japan)
Toshiharu Katayama, Mitsubishi Electric Corp. (Japan)
Hidekazu Yamamoto, Mitsubishi Electric Corp. (Japan)
Yoji Mashiko, Mitsubishi Electric Corp. (Japan)


Published in SPIE Proceedings Vol. 3510:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV
Sharad Prasad; Hans-Dieter Hartmann; Tohru Tsujide, Editor(s)

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