Share Email Print
cover

Proceedings Paper

Shorter failure analysis using a new application of IDDQ for defect localization in ICs
Author(s): Romain Desplats; Bertrand Fougnie; Philippe Perdu; Jamel Benbrik; Francois Marc; Yves Danto
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. Duration and accuracy of localization have a direct impact on the cost of failure analysis. Faster, better localization means shorter failure analysis and turn around time which in turn impacts the yield and reliability of IC production lines. To respond to this challenge, a new application of IDDQ tests has been developed to accelerate the localization task and to directly impact IC production yields and reliability. In this paper, we will present a novel voltage contrast method for high speed defect localization. Using the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located using only a failed circuit. Comparing the equipotential line with the fault simulator output, the site of the simulated defect corresponding to the physical failure can be extracted, and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.

Paper Details

Date Published: 28 August 1998
PDF: 7 pages
Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); doi: 10.1117/12.324368
Show Author Affiliations
Romain Desplats, CNES-SOREP and Univ. de Bordeaux I (France)
Bertrand Fougnie, CNES-SOREP (France)
Philippe Perdu, CNES-SOREP (France)
Jamel Benbrik, CNES-SOREP and Univ. de Bordeaux I (France)
Francois Marc, Univ. de Bordeaux I (France)
Yves Danto, Univ. de Bordeaux I (France)


Published in SPIE Proceedings Vol. 3510:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV
Sharad Prasad; Hans-Dieter Hartmann; Tohru Tsujide, Editor(s)

© SPIE. Terms of Use
Back to Top