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Proceedings Paper

Stepper NA/PC optimization DOE for i-line masking
Author(s): Chung Yih Lee; Wei Wen Ma; Alex Tsun-Lung Cheng; Kia Huat Gan
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Paper Abstract

In this paper we present a statistical experiment design for stepper NA/PC optimization. The design starts with 2-level 3-factor full factorial. After optimizing ring width, we further optimize NA/PC with a 3-level design. Two responses of DoF and EL are measured using CD-SEM. Process fluctuation is simulated by using wafers with slightly different resist thickness as replication runs. Special stepper jobfile is created top expose different NA/PC settings on the same wafer at adjacent fields in order to eliminate the bias caused by center-of-edge and wafer-to-wafer variation. Production verification of the DOE results is also reported.

Paper Details

Date Published: 3 September 1998
PDF: 6 pages
Proc. SPIE 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, (3 September 1998); doi: 10.1117/12.324359
Show Author Affiliations
Chung Yih Lee, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Wei Wen Ma, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Alex Tsun-Lung Cheng, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Kia Huat Gan, Chartered Semiconductor Manufacturing Ltd. (Singapore)

Published in SPIE Proceedings Vol. 3507:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV
Anthony J. Toprac; Kim Dang, Editor(s)

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