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Proceedings Paper

Mechanism for QBD failure in poly gates
Author(s): Judith B. Barker; Robert Wu; Richard G. Cosway; Julie Stephens; Rich Cote
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Paper Abstract

One of the most widespread uses of polysilicon in MOS devices is as the gate electrode for transistors. The gates described here are processed via a two stage poly deposition. The first stage is a thin gate poly deposition used as an implant screen for threshold adjust implants followed by a thick gate poly deposition. Soon after on- product measurement was introduce at a thin gate polysilicon deposition, QBD failures became the most frequent failure mode. A cross-functional team discovered the wafers failing for QBD were used as on-product measurement wafers at polysilicon deposition. Process mapping revealed the wafer failures for QBD were always loaded directly next to poly dummy wafers during deposition. TEM of nucleation sites disclosed there is a competing reaction between the poly dummy wafer directly above the product wafer and the product wafer. The silane prefers to react on the dummy wafer, leading to less area coverage on the product wafers, which leads to rougher, larger grains. The preclean process for the thick gate poly deposition uses a HF dip. It was proposed that HF was penetrating more easily into the rougher poly grains during the HF dip, damaging the gate oxide, and subsequently causing shorts.

Paper Details

Date Published: 3 September 1998
PDF: 12 pages
Proc. SPIE 3507, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV, (3 September 1998); doi: 10.1117/12.324333
Show Author Affiliations
Judith B. Barker, Motorola (United States)
Robert Wu, Motorola (United States)
Richard G. Cosway, Motorola (United States)
Julie Stephens, Motorola (United States)
Rich Cote, Motorola (United States)

Published in SPIE Proceedings Vol. 3507:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing IV
Anthony J. Toprac; Kim Dang, Editor(s)

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