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Proceedings Paper

CMOS compatibiltity of high-aspect-ratio micromachining (HARM) in bonded silicon-on-insulator (BSOI)
Author(s): Mark E. McNie; David O. King
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Paper Abstract

In this paper, we review work on a novel low temperature SOI HARM process at the Defence Evaluation and Research Agency (DERA) and its integration with on-chip CMOS electronics -- as part of a fully integrated MEMS process or as 'value-added' post-processing on commercial CMOS wafers. BSOI material was designed for micromachining applications. The SOI layer acted as a device layer while the insulating dielectric acted as an etch stop and as a sacrificial layer. This resulted in a low stress material that was optimized for the sacrificial release process. Trench isolation was achieved by deep dry etching to the buried dielectric. These trenches could be refilled to allow metallization to reach isolated components. Higher temperature refill material could also act as a lateral mechanical anchor for structures that would otherwise be completely undercut and float off during the sacrificial process. Structures with aspect ratios of up to 50:1 have been defined using combinations of photolithography, deposition and dry etching. CMOS transistor and capacitor characteristics were measured before and after SOI HARM processing. No detectable change in their characteristics was found. This process is attractive for many micromachining applications. Prototype micro-inertial devices fabricated in this technology are also presented in this paper.

Paper Details

Date Published: 31 August 1998
PDF: 9 pages
Proc. SPIE 3511, Micromachining and Microfabrication Process Technology IV, (31 August 1998); doi: 10.1117/12.324311
Show Author Affiliations
Mark E. McNie, Defence Evaluation and Research Agency Malvern (United Kingdom)
David O. King, Defence Evaluation and Research Agency Malvern (United Kingdom)

Published in SPIE Proceedings Vol. 3511:
Micromachining and Microfabrication Process Technology IV
James H. Smith, Editor(s)

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