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Proceedings Paper

IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects
Author(s): Imran Hashim; Vikram Pavate; Peijun Ding; Barry Chin; Dirk Brown; Takeshi Nogami
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Paper Abstract

Filling of high aspect ratio vias with electroplated copper requires smooth and continuous seed layer whereas prevention of copper diffusion into the adjacent dielectric requires adequate coverage of the barrier along the via sidewalls. Conventional PVD DC magnetron techniques were found to be inadequate for this application, because of insufficient step coverage especially that of Cu on the sidewalls of the high aspect ratio vias, and its agglomeration into discontinuous islands. Ionized metal plasma (IMP) based PVD technology provided superior step coverage of Ta and Cu because of the directionality of the deposited atoms and utilization of ion bombardment to sputter material from the bottom of the via to the sidewalls, thus yielding continuous and conformal barrier and seed layers. Furthermore, the seed layer morphology especially the roughness of the film on the sidewall was found to be quite sensitive to the deposition temperature. The seed layer thickness and film morphology, as well as other deposition parameters as the ratio of coil RF & target DC plasma powers, Ar sputtering pressure, wafer bias and the Ar sputter etch prior to barrier deposition, were all found to affect the subsequent via filling by electroplating. Optimization of the processes enabled filling of high aspect ratio vias. Manufacturability and the process window for the barrier/seed layer processes was evaluated by extended runs and DOEs. The technology was successfully integrated into a multilevel interconnect scheme utilizing Cu plugs, and Cu damascene lines. The via resistance of the Cu plug using this metallization scheme, was found to be significantly lower than that of W plug currently used for Al interconnects. The cost of ownership (COO) of the IMP Ta/Cu seed layer was determined to be significantly lower compared to the current state-of- the-art IMP Ti/CVD TiN liner for W plug.

Paper Details

Date Published: 4 September 1998
PDF: 7 pages
Proc. SPIE 3508, Multilevel Interconnect Technology II, (4 September 1998); doi: 10.1117/12.324046
Show Author Affiliations
Imran Hashim, Applied Materials, Inc. (United States)
Vikram Pavate, Applied Materials, Inc. (United States)
Peijun Ding, Applied Materials, Inc. (United States)
Barry Chin, Applied Materials, Inc. (United States)
Dirk Brown, Advanced Micro Devices, Inc. (United States)
Takeshi Nogami, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3508:
Multilevel Interconnect Technology II
Mart Graef; Divyesh N. Patel, Editor(s)

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