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Proceedings Paper

0.50-um pitch metal integration in 0.18-um technology
Author(s): Jeffrey R. D. DeBord; Vidyasagar Jayaraman; Melissa M. Hewson; Wei W. Lee; John Robert Ilzhoefer
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Paper Abstract

As metal pitch requirements for 0.18 micrometer generation logic shrink to 0.50 micrometer pitch and below, the capability of 248 nm deep ultraviolet (DUV) lithography is challenged, especially for isolated narrow lines. Standard illumination methods and binary masks do not give acceptable performance on both dense and isolated 0.25 micrometer structures simultaneously. Two methods available to reliably pattern isolated structures with enough depth of focus (DOF) for high volume manufacturing are Optical Proximity Correction (OPC) techniques such as scattering bars and serifs or the addition of a selective size adjust that sizes all isolated narrow leads up to a width with acceptable DOF. The present work will discuss a manufacturable 0.50 micrometer pitch metallization scheme for leading edge logic applications incorporating DUV lithography, an inorganic silicon oxy- nitride (SION) anti-reflective coating (ARC) layer and standard etch chemistries, with a comparison of the performance of scattering bars and selective size adjusts on isolated lines. Results were characterized by SEM cross sections and electrical data extracted from parametric test structures. Also discussed will be a general methodology of implementing elements of OPC with an eye towards robustness, manufacturability and simplicity of implementation.

Paper Details

Date Published: 4 September 1998
PDF: 6 pages
Proc. SPIE 3508, Multilevel Interconnect Technology II, (4 September 1998); doi: 10.1117/12.324041
Show Author Affiliations
Jeffrey R. D. DeBord, Texas Instruments Inc. (United States)
Vidyasagar Jayaraman, Texas Instruments Inc. (United States)
Melissa M. Hewson, Texas Instruments Inc. (United States)
Wei W. Lee, Texas Instruments Inc. (United States)
John Robert Ilzhoefer, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 3508:
Multilevel Interconnect Technology II
Mart Graef; Divyesh N. Patel, Editor(s)

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