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Proceedings Paper

Improved post-etch cleaning of dual-damascene system for 0.18-μm technology
Author(s): Didier Louis; Catherine Peyne; Emile Lajoinie; B. Vallesi; David J. Maloney; Shihying Lee
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Paper Abstract

A key challenge for 0.18 micrometer technology is the interconnect RC delay time, which becomes the limiting factor for device performance. This delay can be reduced by combining the use of a material of low dielectric constant between metal lines and the use of copper, which is a better conductor than aluminum. In this paper some of the difficulties of integrating these types of interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.

Paper Details

Date Published: 4 September 1998
PDF: 8 pages
Proc. SPIE 3508, Multilevel Interconnect Technology II, (4 September 1998); doi: 10.1117/12.324024
Show Author Affiliations
Didier Louis, CEA-LETI (France)
Catherine Peyne, EKC Technology, Inc. (United States)
Emile Lajoinie, SGS-Thomson (France)
B. Vallesi, SGS-Thomson (France)
David J. Maloney, EKC Technology, Inc. (United States)
Shihying Lee, EKC Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 3508:
Multilevel Interconnect Technology II
Mart Graef; Divyesh N. Patel, Editor(s)

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