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Proceedings Paper

VLIW processor architecture adapted to FPAs
Author(s): Laurent Petit; Jean-Didier Legat
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Paper Abstract

A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity.

Paper Details

Date Published: 7 September 1998
PDF: 5 pages
Proc. SPIE 3410, Advanced Focal Plane Arrays and Electronic Cameras II, (7 September 1998); doi: 10.1117/12.324008
Show Author Affiliations
Laurent Petit, Univ. Catholique de Louvain (Belgium)
Jean-Didier Legat, Univ. Catholique de Louvain (Belgium)


Published in SPIE Proceedings Vol. 3410:
Advanced Focal Plane Arrays and Electronic Cameras II
Thierry M. Bernard, Editor(s)

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