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Proceedings Paper

Making the most of 15kλ2 silicon area for a digital retina PE
Author(s): Fabrice Paillet; Damien S. Mercier; Thierry M. Bernard
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Paper Abstract

Lodging a digital processing element (PE) in each pixel of a focal plane array is the challenge to be taken up to get programmable artificial retinas (PAR) that can be used in a large variety of applications. Using semi-static memory and communication structures together with charge sharing based computing circuitry, we elaborate a PE architecture of which the computational power versus area ratio improves over all previously known attempts. A key feature is the ability of neighbor PEs to be gathered into clusters allowing to get virtual memory through multigranularity computation. A 128 X 128 PAR, called PVLSAR 2.2, has been fabricated accordingly with 5 binary registers per PE. Each PE fits within a 15k(lambda) 2 silicon area$LR.

Paper Details

Date Published: 7 September 1998
PDF: 10 pages
Proc. SPIE 3410, Advanced Focal Plane Arrays and Electronic Cameras II, (7 September 1998); doi: 10.1117/12.324004
Show Author Affiliations
Fabrice Paillet, DGA/DCE (United States)
Damien S. Mercier, DGA/DCE (France)
Thierry M. Bernard, DGA/DCE (France)


Published in SPIE Proceedings Vol. 3410:
Advanced Focal Plane Arrays and Electronic Cameras II
Thierry M. Bernard, Editor(s)

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