Share Email Print

Proceedings Paper

High-k scaling for gate insulators: an insightful study
Author(s): Srinath Krishnan; Geoffrey C. Yeap; Bin Yu; Qi Xiang; Ming-Ren Lin
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has called for introduction of high-k materials below the 100 nm technology node due to problems with direct tunneling in SiO2. However, introduction of high-k poses many challenges in the process/materials side in CMOS process integration. Also, there are device scaling issues that are equally important. When k is increased beyond a certain level, unforeseen effects come to play. A phenomenon known as fringing-induced barrier lowering (FIBL) increases Ioff and degrades the subthreshold swing of the device. This paper describes this phenomenon, and provides insight into device scaling with high k materials. A host of other tradeoffs, especially those concerning control of Ioff and speed, are examined using 2-D simulator and analytical models. Suggestions to control FIBL are also detailed.

Paper Details

Date Published: 4 September 1998
PDF: 8 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323991
Show Author Affiliations
Srinath Krishnan, Advanced Micro Devices, Inc. (United States)
Geoffrey C. Yeap, Advanced Micro Devices, Inc. (United States)
Bin Yu, Advanced Micro Devices, Inc. (United States)
Qi Xiang, Advanced Micro Devices, Inc. (United States)
Ming-Ren Lin, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top