Share Email Print

Proceedings Paper

New methodology of simulating pocket-implanted sub-0.18-um CMOS
Author(s): Manoj Mehrotra; Jerry C. Hu; Mahalingam Nandakumar; Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents a new approach to model the pocket implanted transistors for simulating sub-0.18 micrometer CMOS. The simulation approach presented in the prior publications for pocket implanted transistors has limitations in accurately matching the experimental Vt-rolloff and DIBL characteristics for gate lengths in the sub-0.18 micrometer regime. This is due to the fact that the pocket profile used in the prior simulator does not account for the 2-D boron redistribution effect caused by the source/drain extension implant (MDD). The new model incorporates two-dimensional redistribution of pocket caused by the drain extension implant. There are no additional modeling parameters added for the simulations when compared to the previously published model. The calibrated simulator with the new pocket model shows good agreement with the experimental data for 0.10 - 0.18 micrometer technology transistors.

Paper Details

Date Published: 4 September 1998
PDF: 9 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323980
Show Author Affiliations
Manoj Mehrotra, Texas Instruments Inc. (United States)
Jerry C. Hu, Texas Instruments Inc. (United States)
Mahalingam Nandakumar, Texas Instruments Inc. (United States)
Amitava Chatterjee, Texas Instruments Inc. (United States)
Mark Rodder, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top