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Proceedings Paper

Hot-carrier effects in sub-100-nm gate-length N-MOSFETs with thermal and nitrided oxide thickness down to 1.3 nm
Author(s): Geoffrey C. Yeap; Miryeong Song; Qi Xiang; K. Michael Han; Ming-Ren Lin
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Paper Abstract

Device degradation due to hot-carrier injection in sub-100 nm gate length devices has been investigated. 90 nm gate length (CD SEM) N-MOSFETs with 2.2 nm nitrous oxide (Idsat equals 735 uA/micrometer, Idoff equals 1.1 nA/micrometer Vdd equals 1.5 V) are electrically stressed and measured up to 200,000 seconds. Both VgIsubmax and Vg equals Vd stressing conditions at 1.8, 2.0, 2.2 V, 2.5 V and 2.8 V are performed. Contrary to traditional understanding, Vg equals Vd, i.e. channel hot carrier injection CHCI), stress causes more idlin, Idsat, Vt and Gm degradations. Similar trends are observed in NMOS devices fabricated with 1.6 nm thermal and nitrous oxides as well as 1.3 nm nitric oxides. CHCI being a worst case DC hot carrier stress condition for sub-100 nm devices with ultra- thin gate oxides is a gate-length and stress-voltage dependent phenomenon. For 90 nm NMOS devices, VgIsubmax degradation becomes dominant again when stress voltage is 2.0 V or less. For a set stress voltage, e.g. 2.5 V, VgIsubmax degradation is observed to be dominant for gate length (Leff) larger than 130 nm (90 nm). Negligible device degradation (less than 1%) under high uniform gate field tunneling stress suggests lateral electric field is causing the device degradation and CHCI as the dominant stress mechanism in sub-100 nm N-MOSFETs with direct tunneling oxides. Post-stress sub-threshold swing, charge-pumping and DC-current-voltage characterization suggest that stress-generated interface trap is a major cause of device degradation.

Paper Details

Date Published: 4 September 1998
PDF: 6 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323979
Show Author Affiliations
Geoffrey C. Yeap, Advanced Micro Devices, Inc. (United States)
Miryeong Song, Advanced Micro Devices, Inc. (United States)
Qi Xiang, Advanced Micro Devices, Inc. (United States)
K. Michael Han, Advanced Micro Devices, Inc. (United States)
Ming-Ren Lin, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

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