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Proceedings Paper

Sub-100-nm and deep sub-100-nm MOS transistor gate patterning
Author(s): Qi Xiang; Subash Gupta; Chris A. Spence; Bhanwar Singh; Geoffrey C. Yeap; Ming-Ren Lin
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Paper Abstract

This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias process combined with deep ultraviolet (DUV) lithography. In this paper, we report results on BARC effect, uniformity and iso/dense bias, etch selectivity, poly profile sensitivity, endcap pullback and metrology issues. We have achieved pitting free etch for ultra thin gate oxides down to 15 A. Deep sub-100 nm (approximately 50 nm) photo resist lines and deep sub-100 nm (less than 50 nm) poly gates with a good profile have been obtained.

Paper Details

Date Published: 4 September 1998
PDF: 10 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323977
Show Author Affiliations
Qi Xiang, Advanced Micro Devices, Inc. (United States)
Subash Gupta, Advanced Micro Devices, Inc. (United States)
Chris A. Spence, Advanced Micro Devices, Inc. (United States)
Bhanwar Singh, Advanced Micro Devices, Inc. (United States)
Geoffrey C. Yeap, Advanced Micro Devices, Inc. (United States)
Ming-Ren Lin, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

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