Share Email Print

Proceedings Paper

Sub-50-nm PtSi Schottky source/drain MOSFETs
Author(s): Chinlee Wang; John P. Snyder; John R. Tucker
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

PtSi source/drain Schottky barrier MOSFETs have been fabricated at sub-50-nm channel lengths with 19-angstrom gate oxide. These p-channel devices employ gate-induced field emission through the PtSi approximately 0.2-eV hole barrier to achieve current drives of approximately 200 (mu) A/micrometer at supply voltage of 1.0 V. Delay times measured by the CV/I metric extends scaling trends of conventional p-MOSFETs to approximately 2 - 3 ps. Thermal emission over the low Schottky barrier limits on/off currents to approximately 25 - 50 in undoped devices at 300 K, while ratios of approximately 107 are measured at 77 K. On/off ratios at room temperature can be improved to approximately 103 by implanting a thin layer of fully-depleted donors beneath the active region or use of ultra-thin SOI substrates.

Paper Details

Date Published: 4 September 1998
PDF: 4 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323975
Show Author Affiliations
Chinlee Wang, EG&G Reticon (United States)
John P. Snyder, Spinnaker Semiconductor (United States)
John R. Tucker, Univ. of Illinois/Urbana-Champaign (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top