Share Email Print

Proceedings Paper

Impact of silicon-type floating gate on EEPROM performance
Author(s): Karine Ogier-Monnier; Philippe Boivin; Olivier Bonnaud
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In CMOS technology for EEPROM, refractory metal silicide is currently used to shunt the doped polysilicon layer for the floating gate electrode. Due to their manufacturability, tungsten silicide (WSi2) and tantalum silicide (TaSi2) are widely used in integrated circuit manufacturing. In this paper, electrical tests are performed on MOS capacitors and on memory cells. We will compare three types of silicides: TaSi2 deposited by sputtering and WSi2 deposited with two chemistries: the monosilane reduction of tungsten hexafluoride (MS) and the dichlorosilane reduction of tungsten hexafluoride (DCS). Regarding the cycling performance of the memory cell, tantalumsilicide and tungsten silicide DCS are both good candidates for gate material, but in term of data retention results, they are not the best candidates because of their higher charge loss during bake.

Paper Details

Date Published: 4 September 1998
PDF: 7 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323973
Show Author Affiliations
Karine Ogier-Monnier, SGS-Thomson Microelectronics (France)
Univ. de Rennes I (France)
Philippe Boivin, SGS-Thomson Microelectronics (France)
Olivier Bonnaud, Univ. de Rennes I (France)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top