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Proceedings Paper

Optimized shallow trench isolation for sub-0.18-um ASIC technologies
Author(s): Faran Nouri; Olivier Laparra; Harlan Sur; Samar K. Saha; Dipankar Pramanik; Martin Manley
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Paper Abstract

An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.

Paper Details

Date Published: 4 September 1998
PDF: 11 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323962
Show Author Affiliations
Faran Nouri, VLSI Technology, Inc. (United States)
Olivier Laparra, VLSI Technology, Inc. (United States)
Harlan Sur, VLSI Technology, Inc. (United States)
Samar K. Saha, VLSI Technology, Inc. (United States)
Dipankar Pramanik, VLSI Technology, Inc. (United States)
Martin Manley, VLSI Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

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