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Proceedings Paper

Sub-half-micron device fabricated with 2-um generation facilities
Author(s): Kiyoshi Mori
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Paper Abstract

A MOS transistor with a channel length under 0.20 micrometer was developed with the process equipment typically utilized for a conventional 2 micrometer device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2 micrometer planar technology. The capability of having larger W coupled with non- photolithography limited L, gives this vertical MOS transistor great advantages in drain current IDS, transconductance gm, and operation frequency fo over same technology planar transistors.

Paper Details

Date Published: 4 September 1998
PDF: 9 pages
Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); doi: 10.1117/12.323959
Show Author Affiliations
Kiyoshi Mori, Sony Semiconductor Co. (United States)

Published in SPIE Proceedings Vol. 3506:
Microelectronic Device Technology II
David Burnett; Dirk Wristers; Toshiaki Tsuchiya, Editor(s)

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