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Proceedings Paper

Architecture for low-power real-time image analysis using 3D silicon technology
Author(s): Lisa A. McIlrath; Paul M. Zavracky
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Paper Abstract

The technology to build highly integrated 3D computational image sensors by stacking and interconnecting layers of 2D silicon ICs is being developed. Unlike multi-chip module packaging, in which interconnect lines are brought to the periphery of a chip stack to achieve vertical integration, this new technology allows virtually unrestricted placement of vertical vias within the interior of the chip. The goal of this development is to enable high sped, high resolution image processing in compact low power wearable systems that would be coupled with a head-mounted display. Potential applications for these systems include target tracking and image stabilization. In this talk we focus on the architecture of the 3D image sensor, which includes pixel- parallel analog-to-digital conversion and programmable digital processors for pixel and block operations. We show that 3D technology will allow at least an order of magnitude decrease in power dissipation over an equivalent 2D implementation of the architecture.

Paper Details

Date Published: 11 August 1998
PDF: 12 pages
Proc. SPIE 3362, Helmet- and Head-Mounted Displays III, (11 August 1998); doi: 10.1117/12.317431
Show Author Affiliations
Lisa A. McIlrath, Northeastern Univ. (United States)
Paul M. Zavracky, Northeastern Univ. (United States)

Published in SPIE Proceedings Vol. 3362:
Helmet- and Head-Mounted Displays III
Ronald J. Lewandowski; Loran A. Haworth; Henry J. Girolamo, Editor(s)

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