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Proceedings Paper

Line-edge roughness in sub-0.18-um resist patterns
Author(s): Susan C. Palmateer; Susan G. Cann; Jane E. Curtin; Scott P. Doran; Lynn M. Eriksen; Anthony R. Forte; Roderick R. Kunz; Theodore M. Lyszczarz; Margaret B. Stern; Carla M. Nelson-Thomas
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Paper Abstract

We have characterized line-edge roughness in single-layer, top-surface imaging, bilayer and trilayer resist schemes. The results indicate that in dry developed resists there is inherent line-edge roughness which results from the etch mask, resist (planarizing layer) erosion, and their dependence on plasma etch conditions. In top surface imaging the abruptness of the etch mask, i.e., the silylation contrast, and the silicon content in the silylated areas are the most significant contributors to line-edge roughness. Nevertheless, even in the case of a trilayer, where the SiO2 layer represents the near ideal mask, there is still resist sidewall roughness of the planarizing layer observed which is plasma induced and polymer dependent. The mechanism and magnitude of line-edge roughness are different for different resist schemes, and require specific optimization. Plasma etching of silicon, like O2 dry development, contributes to the final line-edge roughness of patterned features.

Paper Details

Date Published: 29 June 1998
PDF: 9 pages
Proc. SPIE 3333, Advances in Resist Technology and Processing XV, (29 June 1998); doi: 10.1117/12.312395
Show Author Affiliations
Susan C. Palmateer, MIT Lincoln Lab. (United States)
Susan G. Cann, MIT Lincoln Lab. (United States)
Jane E. Curtin, MIT Lincoln Lab. (United States)
Scott P. Doran, MIT Lincoln Lab. (United States)
Lynn M. Eriksen, MIT Lincoln Lab. (United States)
Anthony R. Forte, MIT Lincoln Lab. (United States)
Roderick R. Kunz, MIT Lincoln Lab. (United States)
Theodore M. Lyszczarz, MIT Lincoln Lab. (United States)
Margaret B. Stern, MIT Lincoln Lab. (United States)
Carla M. Nelson-Thomas, Motorola and SEMATECH (United States)


Published in SPIE Proceedings Vol. 3333:
Advances in Resist Technology and Processing XV
Will Conley, Editor(s)

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