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Proceedings Paper

Real-time implementation of JPEG encoder/decoder
Author(s): Thomas M. Czyszczon; Roy S. Czernikowski; Muhammad E. Shaaban; Kenneth W. Hsu
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Paper Abstract

With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further plans include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.

Paper Details

Date Published: 18 June 1998
PDF: 12 pages
Proc. SPIE 3422, Input/Output and Imaging Technologies, (18 June 1998); doi: 10.1117/12.311097
Show Author Affiliations
Thomas M. Czyszczon, Rochester Institute of Technology (United States)
Roy S. Czernikowski, Rochester Institute of Technology (United States)
Muhammad E. Shaaban, Rochester Institute of Technology (United States)
Kenneth W. Hsu, Rochester Institute of Technology (United States)

Published in SPIE Proceedings Vol. 3422:
Input/Output and Imaging Technologies
Yusheng Tim Tsai; Teh-Ming Kung; Jan Larsen, Editor(s)

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