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Proceedings Paper

New polysilicon thin-film transistors for leakage reduction
Author(s): In-cha Hsieh; Thomas W. Sigmon
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Paper Abstract

A novel device structure for vertical bottom polysilicon (poly-Si) gate thin film transistors (TFTs) with dual-gate and offset structures is proposed. The new device, double- vertical-channel TFTs (DVC TFTs), allows suppression of leakage current and improvement of the photolithography limitation for large panel fabrication because of a deep- submicrometer channel length determined by the thickness of poly-Si gate. A 0.3 micrometers vertical-channel poly-Si TFTs is demonstrated on oxidized Si wafer. For low temperature poly- Si TFTs, several DVC TFTs processes are developed and demonstrated, including excimer laser annealing for the recrystallization of active layer and dopant activation.

Paper Details

Date Published: 17 June 1998
PDF: 7 pages
Proc. SPIE 3421, Display Technologies II, (17 June 1998); doi: 10.1117/12.311065
Show Author Affiliations
In-cha Hsieh, Everest Technology Inc. (Taiwan)
Thomas W. Sigmon, Lawrence Livermore National Lab. (United States)


Published in SPIE Proceedings Vol. 3421:
Display Technologies II
Fang-Chen Luo; Shin-Tson Wu; Shunsuke Kobayashi, Editor(s)

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