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Proceedings Paper

EUV mask absorber defect size requirement at 100-nm design rules
Author(s): Pei-yang Yan; Guojing Zhang; Jenn Chow; Patrick Kofron; Joseph C. Langston; Harun H. Solak; Patrick A. Kearney; Gregory Frank Cardinale; Kurt W. Berger; Craig C. Henderson
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Paper Abstract

In this paper, the printability of Extreme UV (EUV) mask defects at 100 nm design rule is studied via top surface imaging (TSI) resist process. The EUV mask defect size requirement is determined by taking into account the wafer process critical dimension (CD) variability. In the experiment, a programmed EUV absorber defect mask was first fabricated by subtractive metal patterning on a Mo/Si multilayer-coated silicon wafer substrate. The 10X experimental EUV lithography system with 13.4 nm exposure wavelength and 0.08 NA imaging lens was used to expose the programmed defect mask. The resists CD response to the metal absorber mask defect area is measured under different process conditions, i.e., different exposure doses. It is found that similar to a single-layer DUV resist cases that have been studied before, the EUV resist CD responds to the mask defect area linearly for small mask defects. From such a set of CD-defect response lines, the allowable absorber mask defect requirement is assessed via the statistical explanation of the printable mask defect size, which is tied to the wafer process specifications and the actual wafer process CD controllability. Our results showed that a clear and an opaque intrusion absorber mask defect as small as 60- 80 nm is printable at 100 nm design rules. Based on the statistical defect printability analysis method that we have developed, the printable mask defect size can always be redefined without additional data collection when the process controllability or the process specification changes.

Paper Details

Date Published: 5 June 1998
PDF: 8 pages
Proc. SPIE 3331, Emerging Lithographic Technologies II, (5 June 1998); doi: 10.1117/12.309627
Show Author Affiliations
Pei-yang Yan, Intel Corp. (United States)
Guojing Zhang, Intel Corp. (United States)
Jenn Chow, Intel Corp. (United States)
Patrick Kofron, Intel Corp. (United States)
Joseph C. Langston, Intel Corp. (United States)
Harun H. Solak, Univ. of Wisconsin/Madison (Switzerland)
Patrick A. Kearney, Lawrence Livermore National Lab. (United States)
Gregory Frank Cardinale, Sandia National Labs. (United States)
Kurt W. Berger, Sandia National Labs. (United States)
Craig C. Henderson, Sandia National Labs. (United States)

Published in SPIE Proceedings Vol. 3331:
Emerging Lithographic Technologies II
Yuli Vladimirsky, Editor(s)

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