Proceedings PaperHigh-speed VLSI concentrators for terabit intelligent optical backplanes
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Self-routing `concentrators' are fundamental building blocks of optical switching systems. An N-to-M concentrator can process and extract data packets from N optical channels and forward the packets to M electrical channels, where typically N M. Terabit Optical Backplanes which exploit free-space optical data links, with bandwidths approaching 1 - 10 Terabits per second will require extremely fast self- routing concentrators which can make routing decisions within a few nanoseconds. In this paper, a VLSI analysis of a new circuit called the `Daisy Chain' concentrator is presented. This concentrator has a regular topology suitable for very efficient VLSI layout, which leads to very high clock rates. The analyses are performed using 0.8 micrometers standard cell CMOS technology with the Synopsys CAD tool. The results shows that the proposed concentrator uses substantially less VLSI area from 20 - 50% less in the control logic and up to 150% less on the switching logic than the previous best known concentrator circuit. It also performs significantly faster, ranging from 20 - 40% faster in the control logic and 150 - 300% faster in the switching logic. Using 0.8 micrometers CMOS technology, the proposed concentrator can be used in smart pixel arrays for optical backplanes with clock rates in the range of 500 Mhz. Using faster CMOS or ECL logic, the concentrator can support clock rates in the several Gigahertz range.