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Proceedings Paper

Latency requirements of optical interconnects at different memory hierarchy levels of a computer system
Author(s): Henk Neefs; Pim Van Heuven; Jan M. Van Campenhout
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Paper Abstract

It is the ideal of a computer designer to have a huge, yet very fast memory connected to a uniprocessor core. But in reality, these two requirements, fast and huge, are not reconcilable. For this reason, a memory hierarchy was introduced that consists of very fast and small memory close to the processor core (the registers) but slower and larger memory further away from the processor (Figure 1). When data is needed, it is fetched from the slower memory into faster memory, from which it can be quickly accessed.

Paper Details

Date Published: 22 May 1998
PDF: 4 pages
Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); doi: 10.1117/12.308874
Show Author Affiliations
Henk Neefs, Univ. of Gent (Belgium)
Pim Van Heuven, Univ. of Gent (Belgium)
Jan M. Van Campenhout, Univ. of Gent (Belgium)

Published in SPIE Proceedings Vol. 3490:
Optics in Computing '98
Pierre H. Chavel; David A. B. Miller; Hugo Thienpont, Editor(s)

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