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Proceedings Paper

Efficient and cost-effective photo defect monitoring
Author(s): Khoi A. Phan; Robert Jue Chiu; Shobhana Punjabi; Bhanwar Singh
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Paper Abstract

Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects during the fabrication process. Defect densities are monitored on product wafers to determine whether the line maintains an acceptable yield level and to prevent any catastrophic downfall. However, defect detection is difficult for multilayer devices. A short loop defect monitor is often employed in the Photolithography area for inspection on an automated wafer inspection system like the KLA 213x. This monitor usually uses clean bare Silicon wafers which are processed through a Photocluster cell to define a resist pattern for defect inspection. In order to monitor a large set of equipment and resist types, a large quantity of clean Silicon wafers are required. The reuse of these silicon photo monitor wafers becomes difficult due to particles left on wafers after resist clean. Thus, the cost of daily photo defect monitor for equipment/process control becomes considerable. In this paper, we will discuss reusable thermal oxide test wafers as an alternative solution to Si wafers for a cost effective photo defect monitor. The required oxide thickness for I-line and DUV resists was calculated from Prolith/2 simulation. By using a special clean with Sulfuric Acid/Hydrogen Peroxide mixture (SPM) and followed by an Ammonium Hydroxide/Hydrogen Peroxide mixture (APM) for resist strip, very low particle counts were achieved for oxide substrate and better than those of Silicon wafers. Furthermore, due to low oxide thickness loss per clean cycle (1 - 2 A), oxide test wafers retain the optical characteristics for defect metrology tools to work without any recalibration. This makes the oxide photo defect monitor process very robust and production worthy. KLA defect data on unpatterned and patterned oxide test wafers for 20 or more reworks, will be shown. They will be compared to control Silicon test wafers. Some issues with exposure and focus condition and their effect on KLA defect detection will be discussed. Finally, a simple cost analysis model will show the potential saving benefit of oxide test wafer.

Paper Details

Date Published: 8 June 1998
PDF: 12 pages
Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308785
Show Author Affiliations
Khoi A. Phan, Advanced Micro Devices, Inc. (United States)
Robert Jue Chiu, Advanced Micro Devices, Inc. (United States)
Shobhana Punjabi, Advanced Micro Devices, Inc. (United States)
Bhanwar Singh, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 3332:
Metrology, Inspection, and Process Control for Microlithography XII
Bhanwar Singh, Editor(s)

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