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Proceedings Paper

Competitive assessment of 200-mm epitaxial silicon wafer flatness
Author(s): Howard R. Huff; D. W. McCormack
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Paper Abstract

The flatness data indicates all suppliers are capable of supporting the 250 nm technology generation while several suppliers are already capable of supporting the 180 nm technology generation. It appears that individual parameter 300 mm polished wafer data are comparable with state-of-the- art and, indeed, may even be better than for 200 mm epitaxial wafers. Continued improvements in the control of the magnitude, tolerance and uniformity of silicon wafers is essential. A steep gradient in the learning curve is being pursued by all suppliers, especially for 300 mm wafers. However, it is also critical to balance the ''best wafer possible' against the cost-o-ownership (CoO) opportunity of not driving silicon requirements to the detection limit or ultimate tool resolution but to some less stringent and optimized value.

Paper Details

Date Published: 8 June 1998
PDF: 6 pages
Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308775
Show Author Affiliations
Howard R. Huff, SEMATECH (United States)
D. W. McCormack, SEMATECH (United States)


Published in SPIE Proceedings Vol. 3332:
Metrology, Inspection, and Process Control for Microlithography XII
Bhanwar Singh, Editor(s)

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