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Proceedings Paper

Definition and control of contact holes in a CMP process
Author(s): Christine Wallace; Brian Martin; Graham G. Arthur
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Paper Abstract

Control of contact hole sizes in a sub-half-micron CMOS process using planarisation by resist etch back and chemical mechanical polishing is discussed. The limitations of using top anti-reflective coatings to overcome thin film effects on transparent substrates are calculated by simulation. Use of bottom anti-reflective coatings to improve uniformity in the resist etch back process are described through practical results which additionally show that comparable results are achieved in the chemical mechanical polishing process but in the absence of a bottom anti-reflective coating.

Paper Details

Date Published: 8 June 1998
PDF: 9 pages
Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308772
Show Author Affiliations
Christine Wallace, GEC Plessey Semiconductors Ltd. (France)
Brian Martin, GEC Plessey Semiconductors Ltd. (United Kingdom)
Graham G. Arthur, Rutherford Appleton Lab. (United Kingdom)

Published in SPIE Proceedings Vol. 3332:
Metrology, Inspection, and Process Control for Microlithography XII
Bhanwar Singh, Editor(s)

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